Wafer Space is a very well-funded startup in the Semiconductor Services space. We are looking
for smart and enterprising Physical Design engineers to come join us and get an opportunity to do some cutting edge work and also work in a great environment where work is Always Fun and Exciting.
Duties and Responsibilities
Responsible for Ownership of Multiple blocks of Multi-million gate RTL-GDSII Physical implementation on high
performance/Low power design flows
Tasks includes synthesis, floor planning, place and route, power & signal integrity analysis, timing closure
and physical verification
In addition, high performance/Low power advanced flow & methodology development and vendor tool evaluations
Stock Options and Ownership in Wafer Space
Desired Skills & Experience
2 to 5 years’ experience.
Excellent Communication and Presentation Skills
Candidates must have prior experience in implementation of high-performance, low-power design using latest
Synopsys, Cadence and/or Magma toolsets
Technical depth in the areas of TCL/PERL scripting, partitioning, prototyping flows, synthesis, floor planning,
place and route, power & signal integrity analysis, timing closure and physical verification is a must.
Education Requirements: Bachelor's degree in Electrical Engineering required; Master's degree in
Electrical Engineering preferred.