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SOC Verification Lead 6+ Years Experience
SOC Verification Lead
Job Description
Wafer Space is a very well-funded startup in the Semiconductor Services space. We are looking
for a smart and enterprising leader with expert knowledge in SOC level verification who can help build an SOC verification team and also lead the team and execute projects. Come join us and get an opportunity to do some great work and also work in a great environment where work is Always Fun and Exciting.
Duties and Responsibilities
Help us build an SOC Verification Team. Execute projects for the client. By the main interface between the client and your team.Remuneration
Salary Stock Options and Ownership in Wafer SpaceBenefitsIn addition you will also get the opportunity to learn new languages and methodologies like SV, OVM, VMM and others.
Desired Skills & Experience
6+ years’ experience.Excellent Communication and Presentation SkillsExpert at SOC VerificationExpert in C and Verilog based verificationGood knowledge of protocolsPrior leadership experience not necessary but is desired Ability and desire to learn new methodologies, languages, protocols etc. is required Senior Design Verification Engineer 5+ Years Experience
Job Description
Wafer Space is a very well-funded startup in the Semiconductor Services space. We are looking
for smart and enterprising Senior Design Verification engineers to come join us and get an opportunity to do some cutting edge work and also work in a great environment where work is Always Fun and Exciting.
Duties and Responsibilities
Build SV, SV OVM based environments. Build Specman eRM Based Environments. Verification of IP's using Coverage Driven MethodologyInvolvement in all phases of verification from Test Planning to Environment Building to verification and finally to closure using Code and Functional Coverage
Work with many different networking and other protocols Remuneration
Salary Stock Options and Ownership in Wafer SpaceBenefitsDesired Skills & Experience
5+ years’ experience.Excellent Communication and Presentation SkillsSystem Verilog or Specman expertise low-power design using latest.OVM/eRM expertise highly desiredGood knowledge of protocolsAbility and desire to learn new methodologies, languages, protocols etc.Design Verification Engineer2 to 5 Years Experience
Job Description
Wafer Space is a very well-funded startup in the Semiconductor Services space. We are looking
for smart and enterprising Design Verification engineers to come join us and get an opportunity to do some cutting edge work and also work in a great environment where work is Always Fun and Exciting.
Duties and Responsibilities
Build SV, SV OVM based environments. Build Specman eRM Based Environments.Verification of IP's using Coverage Driven MethodologyInvolvement in all phases of verification from Test Planning to Environment Building to verification and finally to closure using Code and Functional Coverage
Work with many different networking and other protocolsRemuneration
Salary Stock Options and Ownership in Wafer SpaceBenefitsDesired Skills & Experience
2 to 5years’ experience in Design VerificationExcellent Communication and Presentation SkillsSystem Verilog or Specman expertiseOVM/eRM expertise highly desiredGood knowledge of protocols.Ability and desire to learn new methodologies, languages, protocols etcSenior Physical Design Engineer 5+ Years Experience
Job Description
Wafer Space is a very well-funded startup in the Semiconductor Services space. We are looking
for smart and enterprising Senior Physical Design engineers to come join us and get an opportunity to do some cutting edge work and also work in a great environment where work is Always Fun and Exciting.
Duties and Responsibilities
Responsible for Ownership of Chip Level Integration/finishing &multiple blocks of Multi-million gate RTL-GDSII Physical implementation on high performance/Low power design flows.
Tasks includes design Partitioning, Prototyping, synthesis, floor planning, place and route, power & signal integrity analysis, timing closure and physical verification
High performance/Low power advanced flow & methodology development and vendor tool evaluationsIn addition, hiring, training, mentoring & managing junior fellow colleaguesRemuneration
Salary Stock Options and Ownership in Wafer SpaceBenefitsDesired Skills & Experience
5+ years’ experience.Excellent Communication and Presentation SkillsCandidates must have prior experience in implementation of high-performance, low-power design using latest Synopsys, Cadence and/or Magma toolsets.
Technical depth in the areas of TCL/PERL scripting, partitioning, prototyping flows, synthesis, floor planning, place and route, power & signal integrity analysis, timing closure and physical verification is a must.
Education Requirements: Bachelor's degree in Electrical Engineering required; Master's degree in Electrical Engineering preferred.
Physical Design Engineer 2 to 5 Years Experience
Job Description
Wafer Space is a very well-funded startup in the Semiconductor Services space. We are looking
for smart and enterprising Physical Design engineers to come join us and get an opportunity to do some cutting edge work and also work in a great environment where work is Always Fun and Exciting.
Duties and Responsibilities
Responsible for Ownership of Multiple blocks of Multi-million gate RTL-GDSII Physical implementation on high performance/Low power design flows
Tasks includes synthesis, floor planning, place and route, power & signal integrity analysis, timing closure and physical verification
In addition, high performance/Low power advanced flow & methodology development and vendor tool evaluationsRemuneration
Salary Stock Options and Ownership in Wafer SpaceBenefitsDesired Skills & Experience
2 to 5 years’ experience.Excellent Communication and Presentation SkillsCandidates must have prior experience in implementation of high-performance, low-power design using latest Synopsys, Cadence and/or Magma toolsets
Technical depth in the areas of TCL/PERL scripting, partitioning, prototyping flows, synthesis, floor planning, place and route, power & signal integrity analysis, timing closure and physical verification is a must.
Education Requirements: Bachelor's degree in Electrical Engineering required; Master's degree in Electrical Engineering preferred.
Lead DFT Design Engineer7+ years’ experience
Job Description
Wafer Space is a very well-funded startup in the Semiconductor Services space. We are looking
for a smart and enterprising Lead DFT engineerto come join us and get an opportunity to build a DFT team for us.
Duties and Responsibilities
Lead the DFT Team.Help build a new DFT Team. Responsible for Ownership of Multi-million gate SoC level DFT implementation.Tasks includes DFT architecture planning, IO Pin muxing, Post silicon testing/debugging, Scan, MBIST, JTAG, BSR insertion, pattern generation & simulation.
High performance/Low power advanced flow & methodology development and vendor tool evaluationsIn addition, hiring, training, mentoring & managing junior fellow colleagues.Remuneration
Salary Stock Options and Ownership in Wafer SpaceBenefitsDesired Skills & Experience
7+ years’ experience.Excellent Communication and Presentation SkillsExpert in all aspects of DFT.Prior experience leading a DFT team highly desired.Candidates must have prior experience in implementation of high-performance, low-power design using latest mentor, Synopsys and/or cadence toolsets.
Technical depth in the areas of TCL/PERL scripting, DFT Architecture planning, IO Pin muxing, Post silicon testing/debugging, Scan, BIST, JTAG, BSR, ATPG is a must.
DFT Design Engineers 2 to 5 years’ experience
Job Description
Wafer Space is a very well-funded startup in the Semiconductor Services space. We are looking
for smart and enterprising DFT engineers to come join us and get an opportunity to do some cutting edge work and also work in a great environment where work is Always Fun and Exciting.
Duties and Responsibilities
Responsible for Ownership of Multiple blocks of Multi-million gate DFT implementation.Tasks include Scan, MBIST, ATPG pattern generation & simulation. In addition, high performance/Low power advanced flow & methodology development and vendor tool evaluationsRemuneration
Salary Stock Options and Ownership in Wafer SpaceBenefitsDesired Skills & Experience
2 to 5 years’ experience.Excellent Communication and Presentation SkillsCandidates must have prior experience in implementation of high-performance, low-power design using latest mentor, Synopsys and/or cadence toolsets.
Technical depth in the areas of TCL/PERL scripting, Scan, BIST, ATPG is a must. Education Requirements: Bachelor's degree in Electrical Engineering required; Master's degree in Electrical Engineering preferred.
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Copyright @ Wafer Space All Rights Reserved